The vast majority of electrical interconnection systems employed in semiconductor integrated circuits are non-planar. The degree of non-planarity increases as the number of interconnect levels increases. A disadvantage of non-planar systems is that unwanted open circuits may arise as the result of imperfections in metal step coverage. Similarly, weak areas in insulator step coverage can lead to short circuits between different interconnection levels. Photolithographic and etching difficulties in creating narrow conductive lines on rough surfaces severely restrict the density of electronic elements. A planar interconnect system largely overcomes these problems. A relatively easy method for fabricating a planar system is highly desirable.
U.K. Patent 1,286,737 discloses a technique for manufacturing a planar multi-level interconnection system. With reference to FIG. 1, the starting material in U.K. Patent 1,286,737 is a semiconductor body 10 that adjoins an insulating layer 11 having a planar upper surface. A set of openings are etched through layer 11. A metal layer is deposited on insulator 11 so as to fill the openings. The metal layer is then etched in such a manner that metal fills the openings but does not extend outside them. Item 12 indicates one of the portions of the remaining metal.
Another insulating layer 13 having a planar upper surface is deposited on the coplanar layer formed by insulator 11 and metal portion 12. Openings are selectively etched through layer 13. A metal layer is deposited and etched in the same way as the previous metal layer. The portions of the remaining metal, represented by item 14, are coplanar with insulator 13. These steps are repeated to form a third planar layer consisting of an insulating layer 15 and a metal portion 16 followed by a fourth planar layer consisting of an insulating layer 17 and a metal portion 18.
The metal-filled openings in layers 11, 13, 15, and 17 could be either vias or grooves. Herein, a "via" means a hole (including a contact opening) whose length and width are approximately the same. A "groove" has a much greater length than width. If, for example, each opening in layer 11 is a via while each opening in layer 13 is a groove, metal portions 12 and 14 form a first interconnection level. In like manner, metal portions 16 and 18 form a second interconnect level.
The interconnect system of FIG. 1 is extremely attractive. However, U.K. Patent 1,286,737 does not disclose the particular details of the metal deposition/etching steps that enable each of the composite metal/insulating layers to be planar.
Rothman, "Process For Forming Passivated Metal Interconnection System with a Planar Surface," J. Electrochem. Soc.: SOLID-STATE SCI. & TECH., May 1983, pp. 1131-1136, describes lift-off techniques for depositing an aluminum alloy in cavities in an insulating layer so as to create a composite layer having a planar upper surface. While these lift-off techniques provide relatively good planarity, they involve a large number of complicated and difficult process steps. This limits their usefulness.
Low-pressure chemical vapor deposition (LPCVD) of aluminum is a technique of interest. In Levy et al, "Characterization of LPCVD Aluminum for VLSI Processing," J. Electrochem. Soc.: SOILD-STATE SCI. & TECH., September 1984, pp. 2175-2182, LPCVD aluminum from a tri-isobutyl aluminum source was employed to form an aluminum layer on a dielectric having a rough surface topography. The upper surface of the aluminum layer was largely planar. A disadvantage of this technique is that tri-isobutyl aluminum must be handled very carefully.
Aluminum is the prevalent metal used in interconnects. However, the electromigration resistance of aluminum in pure form or when alloyed with small amounts of copper and/or silicon is relatively low. In addition, aluminum readily interdiffuses with silicon. The resulting degradation of silicon/aluminum junctions leads to undesirably rapid device failure. It does not appear that pure aluminum or conventional aluminum alloys will be capable of meeting the performance requirements for stringent future applications.
A promising interconnect candidate is tungsten whose electromigration resistance is highly superior to that of aluminum. Tungsten has a fairly low resistivity, a high reaction temperature with silicon, a high activation energy, and a high melting temperature. In addition, tungsten acts as a diffusion barrier to silicon and can be readily etched with wet chemicals or plasmas.
A conventional way of depositing tungsten is by LPCVD in which tungsten is supplied by hydrogen reduction of tungsten hexafluoride. The deposition can be highly selective in that tungsten nucleates on certain conductors and semiconductors in preference to insulators. See Broadbent et al, "Selective Low Pressure Chemical Vapor Deposition of Tungsten," J. Electrochem. Soc.: SOLID-STATE SCI. & TECH., June 1984, pp. 1427-1433. Also see Saraswat et al, "Selective CVD of Tungsten for VLSI Technology," Procs. 2nd Int'l Symp. VLSI Sci. & Tech., Vol. 84-7, 1984, pp. 409-419.
Smith, "CVD Tungsten Contact Plugs by In Situ Deposition and Etchback," Procs. 2nd Int'l IEEE VLSI Multilev. Intercon. Conf., 25-26 June 1985, pp. 350-356, describes the use of non-selectively deposited tungsten for via filling. Smith discusses vias (including contact holes) but actually performed his studies on grooves (or trenches). FIGS. 2a-2c show his processing steps. Referring to FIG. 2a, Smith started with a monocrystalline silicon substrate 20 that adjoined a layer 21 of silicon dioxide having a planar upper surface. A groove 22 having nearly vertical sidewalls was etched through layer 21. The aspect ratio--i.e., groove depth divided by groove width--was slightly less than 1
To promote adhesion while avoiding the selective deposition characteristic of tungsten, a thin layer 23 of tungsten silicide was deposited on the structure. A much thicker layer 24 of tungsten with a small percentage of silicon was deposited on layer 23. Both depositions were performed by LPCVD using a vapor consisting of WF.sub.6, H.sub.2, and SiH.sub.4 in which the ratio of tungsten to silicon in each of layers 23 and 24 was controlled by adjusting the WF.sub.6 flow rate. The upper surface of layer 24 was nearly planar as indicated in FIG. 2b. However, a void 25 occurred in layer 24 at the location of groove 22. I believe that void 25 was produced because the silane (SiH.sub.4) caused the hydrogen to reduce the tungsten hexafluoride in the vapor area away from the deposition surfaces. The tungsten thereby accumulated at a lower rate in the more highly shadowed areas in groove 22.
A plasma etch was performed to remove the material of layers 23 and 24 down to the upper surface of insulator 21 as indicated in FIG. 2c. Items 23' and 24' respectively indicate the remaining portions of layers 23 and 24. Void 25 opened into a slot 25' at the top of W portion 24'. Due to the difficulties that would be encountered in providing step coverage on slot 25', its presence is undesirable.